<html><head><meta http-equiv="content-type" content="text/html; charset=utf-8"></head><body style="overflow-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;"><meta http-equiv="content-type" content="text/html; charset=utf-8"><div style="overflow-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;"><meta http-equiv="Content-Type" content="text/html; charset=utf-8"><div style="word-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;"><div id="divtagdefaultwrapper" dir="ltr"><div style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;">INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN (ISLPED) 2023</div><p style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;"> </p><div style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;"> --- ISLPED 2023 CALL FOR PAPERS ---</div><div style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;"> <a href="http://www.islped.org/">http://www.islped.org</a>, Twitter: @islped</div><p style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;"> </p><div style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;">Conference date: August 7–8, 2023</div><div style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;">Location: TU Wien, Vienna, Austria </div><p style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;"> </p><div style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;">IMPORTANT DATES</div><div style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;">Abstract registration: March 6, 2023, at 11:59pm PST</div><div style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;">Full paper: March 13, 2023, at 11:59pm PST</div><div style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;">Invited Talk, Panel, and Embedded Tutorial Proposals: April 10, 2023</div><div style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;">Notification of Paper Acceptance: May 22, 2023</div><div style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;">Submission of Camera-Ready Papers: June 19, 2023</div><p style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;"> </p><div style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;">The International Symposium on Low Power Electronics and Design (ISLPED) is the premier forum for presentation of innovative research in all aspects of low power electronics and design, ranging from process technologies and analog/digital circuits, simulation and synthesis tools, AI/ML-enhanced EDA/CAD, system-level design, and optimization, to system software and applications. Specific topics include, but are not limited to, the following three main tracks and sub-areas:</div><p style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;"> </p><div style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;">1. Technology, Circuits, and Architecture</div><div style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;">1.1. Technologies</div><div style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;">Low-power technologies for device, interconnect, logic, memory, 2.5/3D, cooling, harvesting, sensors, optical, printable, biomedical, battery, and alternative energy storage devices and technology enablers for </div><div style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;">non-Boolean and quantum/quantum-inspired compute models.</div><p style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;"> </p><div style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;">1.2. Circuits</div><div style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;">Low-power circuits for logic, memory, reliability, yield, clocking, resiliency, near-/sub-threshold, and assist schemes; Low-power analog/mixed-signal circuits for wireless, RF, MEMS, AD/DA Converters, I/O, PLLs/DLLS, imaging and DC-DC converters; Energy-efficient circuits for emerging applications (e.g., biomedical, in-vitro sensing, autonomous), circuits using emerging technologies; Cryogenic circuits. Design technology co-optimization (DTCO) for low power. </div><p style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;"> </p><div style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;">1.3. Logic and Architecture</div><div style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;">Low-power logic and microarchitecture for SoC designs, processor cores (compute, graphics, and other special purpose cores), cache, memory, arithmetic/signal processing, cryptography, variability, asynchronous design, and non-conventional computing. System technology co-optimization (STCO) for low power.</div><p style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;"> </p><div style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;">2. EDA, Systems, and Software</div><div style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;">2.1. CAD Tools and Methodologies</div><div style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;">CAD tools, methodologies, and AI/ML-based approaches for low-power and thermal-aware design. AI/ML for acceleration of circuit simulation and IP block design convergence. Power estimation, optimization, reliability, and variation impact on power optimization at all levels of design abstraction: physical, circuit, gate, register transfer, behavior, and algorithm.</div><p style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;"> </p><div style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;">2.2. Systems and Platforms</div><div style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;">Low-power, power-aware, and thermal-aware system design including data centers, SoCs, embedded systems, Internet-of-Things (IoT), wearable computing, body-area networks, wireless sensor networks, and system-level power implications due to reliability and variability. Applications of AI/ML-based solutions and brain-inspired computing to power-aware system and platform design.</div><p style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;"> </p><div style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;">2.3. Software and Applications</div><div style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;">Energy-efficient, energy/thermal-aware software and application design, including scheduling and management, power optimization through HW/SW codesign, and emerging low-power AI/ML applications.</div><p style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;"> </p><div style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;">3. Crosscutting Topics</div><div style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;">3.1. AI/ML Hardware</div><div style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;">Low-power AI/ML HW techniques including approximations, application driven optimizations, in-memory/energy-efficient accelerations, and neuromorphic computing; Energy-efficient AI/ML HW using emerging technologies (including quantum computing).</div><p style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;"> </p><div style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;">3.2. Hardware and System Security</div><div style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;">Low-power hardware security primitives (PUF, TRNG, cryptographic/post-quantum cryptographic accelerators), nano-electronics security, supply chain security, IoT security and AI/ML security; Energy-efficient approaches to system security.</div><p style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;"> </p><div style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;">4. Industrial Design Track</div><div style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;">ISLPED’23 solicits papers for an “Industrial Design” track to reinforce interaction between the academic research community and industry. Industrial Design track papers have the same submission deadline as regular papers and should focus on similar topics but are expected to provide a complementary perspective to academic research by focusing on challenges, solutions, and lessons learnt while implementing industrial-scale designs.</div><p style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;"> </p><div style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;">Submissions (not published/accepted/under review by another journal, conference, symposium, or workshop) should be full-length papers of up to 6 pages (PDF format, double-column, US letter size, using the IEEE Conference format, available at (<a href="https://www.ieee.org/conferences/publishing/templates.html">https://www.ieee.org/conferences/publishing/templates.html</a>) including all illustrations, tables, references, and an abstract of no more than 250 words. Submissions must be anonymous. Submissions failing above requirements will be automatically rejected. Accepted papers will be submitted to the IEEE Xplore Digital Library and the ACM Digital Library. ISLPED’23 will present three Best Paper Awards based on the ratings of reviewers and a panel of judges.</div><p style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;"> </p><div style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;">ISLPED also features a Low Power Design Contest with live demonstrations and awards. Submissions are due on May 15, 2023. More details will soon be available on the conference web page. </div><div style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;">There will be several invited talks by industry and academic thought leaders on key issues in low power electronics and design. The Symposium may also include embedded tutorials to provide attendees with the necessary background to follow recent research results, as well as panel discussions on future directions in low power electronics and design. Proposals for invited talks, embedded tutorials, and panels should be sent by email to the ISLPED’23 Technical Program Co-Chairs, Umit Ogras (<a href="mailto:uogras@wisc.edu">uogras@wisc.edu</a>) and Pascal Meinerzhagen (<a href="mailto:pascal.a.meinerzhagen@intel.com">pascal.a.meinerzhagen@intel.com</a>) by the deadline listed above.</div><div style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;">Participants interested in exhibiting at the Symposium should contact the General Co-Chairs by May 1, 2023.</div><div style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;"><br></div><div style="font-family: Calibri, sans-serif; font-size: 11pt; margin: 0in;"><br></div><p style="margin: 0in;"><font face="Calibri, sans-serif"><span style="font-size: 14.666667px;"></span></font></p></div></div></div></body></html>